In PLL's it is quite common to use fractional relationships between the various frequencies, for example, for use with Forward Error Correction (FEC). The output frequency may be equal to M/N times the input frequency with M=255 and N=237. There are a few common methods to implement this fractional relationship, but those are in reality hampered by rather severe limitations in the final performance.
In generic block diagrams there are two that typically will be used to generate an output frequency that is M/N times the input frequency. There are other implementations possible if M/N can be simplified by getting rid of common denominators of M and N, but that would of course be equivalent to rewriting the M/N fraction to a simpler fraction.
The first block diagram shown in FIG. 1 shows a pre-division by N, so that the 1/N of M/N is attained. The PLL has an M divider in the feedback, implying that the effective transfer of the loop only is M multiplication for frequency. Thus the output will run on M/N.
The disadvantage of this approach is that the edges from input signal are not well applied. The phase detector does not receive every edge from the input signal, but only 1 out of every N signals (the divider blocks the other edges so that their precise edge information gets lost). This implies:                a) The frequency into the phase detector is lower, and so must the maximum bandwidth of the PLL transfer be lower.        b) The reduced bandwidth is more difficult to implement. Typical filters will use a resistive element and a capacitive element, and a reduced bandwidth will typically increase the capacitor, up to a level where for instance integration is not feasible any more.        c) The reduced bandwidth will decrease the suppression of noise from charge pump and VCO.        d) In short: best overall jitter performance suffers from the N pre-division.        
In the second block diagram shown in FIG. 2, the division is done after the PLL. Now the PLL runs with more edges being applied to the PLL, so that in a general sense the quality of the PLL remains constant without extra design effort in the charge pump, filter, VCO and the like. However, the cost is now that the output of the VCO or CCO is now running on an N times higher frequency. The disadvantages are apparent:                a) There is a fair chance the VCO frequencies are no longer feasible. For example, consider the case of an input frequency of 16.384 MHz, N equal to 237 and M equal to 255. The real output frequency is still low (about 17.628 MHz), but now the VCO is required to run 4177.92 MHz, which is not trivial in a standard CMOS process. Of course the numbers can easily become even more extreme.        b) Dividers that divide from the extremely high VCO frequency to lower frequencies become difficult to design.        c) The power will rise due to the higher frequency requirement. Depending on implementation this may reduce the quality. For instance in an integrated VCO the higher power consumption will influence other VCO's in the system.        
In short, both traditional systems have their problems, and it would be attractive to have an alternative technique that does not have same limitations.